Parameter   Nominal             FS   SF   SS   FF
  c018bcd_gen2_v1d6_usage.scs   tt_lib             fs_lib   sf_lib   ss_lib   ff_lib
  c018bcd_gen2_v1d6_usage.scs   pre_simu             nom   nom   nom   nom
  param_test                 <unspecified section>   <unspecified section>   <unspecified section>   <unspecified section>
Test Output Nominal Spec Nominal Spec Weight Pass/Fail Min Max FS Spec FS SF Spec SF SS Spec SS FF Spec FF
                                 
THESIS:TB_TOP_64_64_8:1 /clk                              
THESIS:TB_TOP_64_64_8:1 /EN                              
THESIS:TB_TOP_64_64_8:1 /RW                              
THESIS:TB_TOP_64_64_8:1 /X_ADDRESS_IN<2:0>                              
THESIS:TB_TOP_64_64_8:1 /Y_ADDRESS_IN<5:0>                              
THESIS:TB_TOP_64_64_8:1 /reset                              
THESIS:TB_TOP_64_64_8:1 /Z_BUS<7:0>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/SA_IN<1:8>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/SA_IN<9:16>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/SA_VO<1>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/net1<0>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/SA_VO<2>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/net1<1>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/SA_VO<3>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/net1<2>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/SA_VO<4>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/net1<3>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/SA_VO<5>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/net1<4>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/SA_VO<6>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/net1<5>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/SA_VO<7>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/net1<6>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/SA_VO<8>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/net1<7>                              
THESIS:TB_TOP_64_64_8:1 /TOP/Z_SA<0>                              
THESIS:TB_TOP_64_64_8:1 /TOP/Z_SA<1>                              
THESIS:TB_TOP_64_64_8:1 /TOP/Z_SA<2>                              
THESIS:TB_TOP_64_64_8:1 /TOP/Z_SA<3>                              
THESIS:TB_TOP_64_64_8:1 /TOP/Z_SA<4>                              
THESIS:TB_TOP_64_64_8:1 /TOP/Z_SA<5>                              
THESIS:TB_TOP_64_64_8:1 /TOP/Z_SA<6>                              
THESIS:TB_TOP_64_64_8:1 /TOP/Z_SA<7>                              
THESIS:TB_TOP_64_64_8:1 /P<55>                              
THESIS:TB_TOP_64_64_8:1 /P<54>                              
THESIS:TB_TOP_64_64_8:1 /P<53>                              
THESIS:TB_TOP_64_64_8:1 /P<52>                              
THESIS:TB_TOP_64_64_8:1 /P<51>                              
THESIS:TB_TOP_64_64_8:1 /P<50>                              
THESIS:TB_TOP_64_64_8:1 /P<49>                              
THESIS:TB_TOP_64_64_8:1 /P<48>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/N<56>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/N<55>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/N<54>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/N<53>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/N<52>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/N<51>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/N<50>                              
THESIS:TB_TOP_64_64_8:1 /TOP/RRAM_ANALOG/N<49>                              
THESIS:TB_TOP_64_64_8:1 READ_2   10       10 14   10   10   10   14
THESIS:TB_TOP_64_64_8:1 WRITE_1_7 < -2.31 -2.843 < (-0.7 * VAR("VDDW"))   pass -3.064 -2.546 < -2.31 -2.923 < -2.31 -2.756 < -2.31 -2.546 < -2.31 -3.064
THESIS:TB_TOP_64_64_8:1 WRITE_1_6 > 2.31 2.578 > (0.7 * VAR("VDDW"))   pass 2.519 2.621 > 2.31 2.6 > 2.31 2.544 > 2.31 2.519 > 2.31 2.621
THESIS:TB_TOP_64_64_8:1 WRITE_1_5 < -2.31 -2.826 < (-0.7 * VAR("VDDW"))   pass -3.054 -2.534 < -2.31 -2.904 < -2.31 -2.739 < -2.31 -2.534 < -2.31 -3.054
THESIS:TB_TOP_64_64_8:1 WRITE_1_4 > 2.31 2.578 > (0.7 * VAR("VDDW"))   pass 2.518 2.619 > 2.31 2.6 > 2.31 2.544 > 2.31 2.518 > 2.31 2.619
THESIS:TB_TOP_64_64_8:1 WRITE_1_3 < -2.31 -2.828 < (-0.7 * VAR("VDDW"))   pass -3.056 -2.535 < -2.31 -2.907 < -2.31 -2.741 < -2.31 -2.535 < -2.31 -3.056
THESIS:TB_TOP_64_64_8:1 WRITE_1_2 > 2.31 2.579 > (0.7 * VAR("VDDW"))   pass 2.519 2.62 > 2.31 2.601 > 2.31 2.544 > 2.31 2.519 > 2.31 2.62
THESIS:TB_TOP_64_64_8:1 WRITE_1_1 < -2.31 -2.832 < (-0.7 * VAR("VDDW"))   pass -3.06 -2.535 < -2.31 -2.911 < -2.31 -2.743 < -2.31 -2.535 < -2.31 -3.06
THESIS:TB_TOP_64_64_8:1 WRITE_1_0 > 2.31 2.594 > (0.7 * VAR("VDDW"))   pass 2.534 2.628 > 2.31 2.616 > 2.31 2.565 > 2.31 2.534 > 2.31 2.628
THESIS:TB_TOP_64_64_8:1 WRITE_2_7 > 2.31 2.594 > (0.7 * VAR("VDDW"))   pass 2.53 2.622 > 2.31 2.613 > 2.31 2.562 > 2.31 2.53 > 2.31 2.622
THESIS:TB_TOP_64_64_8:1 WRITE_2_6 < -2.31 -2.84 < (-0.7 * VAR("VDDW"))   pass -3.063 -2.547 < -2.31 -2.916 < -2.31 -2.751 < -2.31 -2.547 < -2.31 -3.063
THESIS:TB_TOP_64_64_8:1 WRITE_2_5 > 2.31 2.58 > (0.7 * VAR("VDDW"))   pass 2.51 2.616 > 2.31 2.603 > 2.31 2.538 > 2.31 2.51 > 2.31 2.616
THESIS:TB_TOP_64_64_8:1 WRITE_2_4 < -2.31 -2.84 < (-0.7 * VAR("VDDW"))   pass -3.064 -2.548 < -2.31 -2.917 < -2.31 -2.751 < -2.31 -2.548 < -2.31 -3.064
THESIS:TB_TOP_64_64_8:1 WRITE_2_3 > 2.31 2.581 > (0.7 * VAR("VDDW"))   pass 2.51 2.617 > 2.31 2.603 > 2.31 2.54 > 2.31 2.51 > 2.31 2.617
THESIS:TB_TOP_64_64_8:1 WRITE_2_2 < -2.31 -2.842 < (-0.7 * VAR("VDDW"))   pass -3.066 -2.55 < -2.31 -2.92 < -2.31 -2.753 < -2.31 -2.55 < -2.31 -3.066
THESIS:TB_TOP_64_64_8:1 WRITE_2_1 > 2.31 2.583 > (0.7 * VAR("VDDW"))   pass 2.508 2.617 > 2.31 2.605 > 2.31 2.54 > 2.31 2.508 > 2.31 2.617
THESIS:TB_TOP_64_64_8:1 WRITE_2_0 < -2.31 -2.862 < (-0.7 * VAR("VDDW"))   pass -3.079 -2.574 < -2.31 -2.944 < -2.31 -2.774 < -2.31 -2.574 < -2.31 -3.079
THESIS:TB_TOP_64_64_8:1 READ_1_0   1.799 > 1.5   pass 1.799 1.799   1.799   1.799   1.799   1.799
THESIS:TB_TOP_64_64_8:1 READ_1_1   -8.992u < 0.3   fail -8.992u 1.799   1.799   -1.14u   -6.757u   1.799
THESIS:TB_TOP_64_64_8:1 READ_1_2   1.799 > 1.5   pass 1.799 1.799   1.799   1.799   1.799   1.799
THESIS:TB_TOP_64_64_8:1 READ_1_3   28.7u < 0.3   pass -4.12u 28.7u   -4.12u   -678n   645n   845.7n
THESIS:TB_TOP_64_64_8:1 READ_1_4   1.799 > 1.5   pass 1.799 1.799   1.799   1.799   1.799   1.799
THESIS:TB_TOP_64_64_8:1 READ_1_5   -9.643u < 0.3   pass -9.643u 36.78u   4.148u   -972.1n   11.27u   36.78u
THESIS:TB_TOP_64_64_8:1 READ_1_6   1.799 > 1.5   pass 1.799 1.799   1.799   1.799   1.799   1.799
THESIS:TB_TOP_64_64_8:1 READ_1_7   -15.98u < 0.3   pass -15.98u 5.641u   4.132u   4.144u   -14.16u   5.641u
THESIS:TB_TOP_64_64_8:1 READ_2_0   46.26u < 0.3   pass -29.7u 46.26u   13.41u   -4.064u   -12.51u   -29.7u
THESIS:TB_TOP_64_64_8:1 READ_2_1   1.799 > 1.5   pass 1.799 1.799   1.799   1.799   1.799   1.799
THESIS:TB_TOP_64_64_8:1 READ_2_2   65.93u < 0.3   fail 4.805u 1.799   10.99u   61.16u   4.805u   1.799
THESIS:TB_TOP_64_64_8:1 READ_2_3   1.799 > 1.5   pass 1.799 1.799   1.799   1.799   1.799   1.799
THESIS:TB_TOP_64_64_8:1 READ_2_4   -5.11u < 0.3   fail -13.77u 1.799   8.747u   -13.77u   6.125u   1.799
THESIS:TB_TOP_64_64_8:1 READ_2_5   1.799 > 1.5   pass 1.799 1.799   1.799   1.799   1.799   1.799
THESIS:TB_TOP_64_64_8:1 READ_2_6   -2.38u < 0.3   fail -2.38u 1.799   1.799   5.233u   4.185u   1.799
THESIS:TB_TOP_64_64_8:1 READ_2_7   1.799 > 1.5   pass 1.799 1.799   1.799   1.799   1.799   1.799
THESIS:TB_TOP_64_64_8:1 READ_1   5       5 7   7   5   5   7


Created on 8 Aug 2021 08:24:47 by Dimitris Antoniadis (da220).